This invention relates generally to linear electrical circuits, and more particularly the invention relates to a CMOS amplifier circuit having enhanced current sinking and capacitance load driving capability.
FIGS. 1A and 1B are schematics of a prior-art output stage circuit of an operational amplifier. An input signal is applied to the bases of two NPN transistors Q1 and Q2 which are connected between a positive potential (V+) and the inputs to an operational amplifier 10 (FIG. 1A). The output of amplifier 10 is connected to the gate of an MOS current sink transistor M7 which is serially connected with transistor Q2 between the positive and negative voltage potentials, V+ and V-, with the common terminal being the output of the amplifier stage. With reference to FIG. 1B, the differential amplifier 10 comprises two CMOS transistor pairs including p-channel transistors M3 and M4 and n-channel transistors M5 and M6. The emitter of transistor Q1 is connected to the gate of transistor M3, and the emitter of transistor Q2 is connected to the gate of transistor M4. A fixed current source, I1, serially connects transistor Q1 to the V- potential, while the current sink transistor M7 serially connects transistor Q2 to the V- potential.
This circuit provides low output impedance and delivers high output current to a load. However, a major shortcoming of the circuit is excessive phase shift when driving a capacitive load and when sinking moderate current at the same time. This presents a potential stability problem and oscillation of the amplifier. More particularly, when the output stage circuit sinks current from the load, a differential voltage, .DELTA.V.sub.ba =V.sub.b -Va, develops between node a and node b and raises the voltage at node c high enough for transistor M7 to sink the output current. To increase the voltage at node c, the node a voltage has to become more negative than the voltage at node b. Since the bases of transistors Q1 and Q2 are tied together, the base-to-emitter bias voltage V.sub.BE of transistor Q2 is smaller than that of transistor Q1 by the amount of .DELTA.V.sub.ba. With transistor Q1 conducting a constant current I1, the reduction of V.sub.BE bias voltage of transistor Q2 results in Q2 conducting less current than normal when not sinking or delivering output current. Since the transconductance of MOS transistors is normally low, the .DELTA.V.sub.ba can become so large for a moderate output sinking current that transistor Q2 conducts extremely low current and contributes excessive phase shift to the signal path, particularly when driving a capacitive load.